Event Id	Proper Counters		Comments
[1m0xffff[0m		OS_Timer		Timer
[1m0x3[0m		PMN0,PMN1,PMN2,PMN3	Cycle Count
[1m0x5[0m		PMN0			DCache Read Hit
[1m0x9[0m		PMN0,PMN1		DCache Read Miss
[1m0x11[0m		PMN0			DCache Write Hit
[1m0x21[0m		PMN0			DCache Write Miss
[1m0x41[0m		PMN0			Retired Instruction
[1m0x401[0m		PMN0			MMU Bus Request (Read Latency)
[1m0x801[0m		PMN0			ICache Bus Request (Read Latency)
[1m0x1001[0m		PMN0			WB Bus Request (Write Latency)
[1m0x2001[0m		PMN0			Hold LDM/STM
[1m0x40001[0m		PMN0			Data Write Access Count
[1m0x80001[0m		PMN0			Data Read Access Count
[1m0x1000001[0m	PMN0			SIMD Cycle Count
[1m0x2000001[0m	PMN0			Predicted Branch Count
[1m0x20000001[0m	PMN0,PMN1		L2C Write Hit
[1m0x40000001[0m	PMN0,PMN1		L2C Write Miss
[1m0x80000001[0m	PMN0			L2C Read Count
[1m0x5[0m		PMN1			ICache Read Miss
[1m0x11[0m		PMN1			DCache Write Miss
[1m0x21[0m		PMN1			ITLB Miss
[1m0x41[0m		PMN1			Single Issue
[1m0x101[0m		PMN1			Branch Retired
[1m0x201[0m		PMN1			ROB Full
[1m0x401[0m		PMN1			MMU Read Beat
[1m0x801[0m		PMN1			ICache Read Beat
[1m0x8001[0m		PMN1			Hold IS
[1m0x1001[0m		PMN1			WB Write Beat
[1m0x10001[0m		PMN1			Data Read Access Count
[1m0x1000001[0m	PMN1			SIMD Retired Instructions
[1m0x2000001[0m	PMN1			SIMD Store FIFO Full
[1m0x80000001[0m	PMN1			L2C Latency
[1m0x9[0m		PMN2			DCache Access
[1m0x11[0m		PMN2			DTLB Miss
[1m0x101[0m		PMN2			Branch Predict Miss
[1m0x201[0m		PMN2			WB Write Beat
[1m0x401[0m		PMN2			A1 Stall
[1m0x801[0m		PMN2			DCache Read Latency
[1m0x1001[0m		PMN2			DCache Write Latency
[1m0x10001[0m		PMN2			BIU Simultaneous Access
[1m0x1000001[0m	PMN2			SIMD Hold IS
[1m0x2000001[0m	PMN2			SIMD Instr Buffer Full
[1m0x20000001[0m	PMN2,PMN3		L2C Read Hit
[1m0x40000001[0m	PMN2,PMN3		L2C Read Miss
[1m0x5[0m		PMN3			DCache Read Miss
[1m0x9[0m		PMN3			DCache Write Miss
[1m0x11[0m		PMN3			TLB Miss
[1m0x101[0m		PMN3			Branches Taken
[1m0x201[0m		PMN3			WB Full
[1m0x801[0m		PMN3			DCache Read Beat
[1m0x1001[0m		PMN3			DCache Write Beat
[1m0x10001[0m		PMN3			BIU Any Access
[1m0x400001[0m	PMN3			Data Write Access Count
[1m0x1000001[0m	PMN3			SIMD Hold Writeback Stage
[1m0x2000001[0m	PMN3			SIMD Retire FIFO Full
[1m0x1D[0m		MC0,MC1,MC2,MC3		Auto-refresh (non-idle)
[1m0x1C[0m		MC0,MC1,MC2,MC3		Auto-refresh (all)
[1m0x1A[0m		MC0,MC1,MC2,MC3		Write request
[1m0x19[0m		MC0,MC1,MC2,MC3		Read request
[1m0x18[0m		MC0,MC1,MC2,MC3		All data request
[1m0x16[0m		MC0,MC1,MC2,MC3		Write command
[1m0x15[0m		MC0,MC1,MC2,MC3		Read command
[1m0x14[0m		MC0,MC1,MC2,MC3		Read + Write command
[1m0x10[0m		MC0,MC1,MC2,MC3		ACTIVE command
[1m0xe[0m		MC0,MC1,MC2,MC3		PRECHARGE command (non-data)
[1m0xd[0m		MC0,MC1,MC2,MC3		PRECHARGE command (data)
[1m0xc[0m		MC0,MC1,MC2,MC3		PRECHARGE command (all)
[1m0x4[0m		MC0,MC1,MC2,MC3		Non-idle cycles with no data bus utilization
[1m0x3[0m		MC0,MC1,MC2,MC3		(reserved) Non-idle cycles waiting for tWTR
[1m0x2[0m		MC0,MC1,MC2,MC3		Non-idle cycles when waiting for tRFC
[1m0x1[0m		MC0,MC1,MC2,MC3		Idle cycles (Memory Controller pipeline empty)
[1m0x0[0m		MC0,MC1,MC2,MC3		Clock
